Conventional memory circuits which utilize static memory cells, such circuits including static random access memories (SRAMs), FIFOs, dual-port memories, and microprocessors and other logic devices with such memory embedded therein, are generally organized in rows and columns. In these conventional memories, a row select line, generally decoded from a row address value, connects each of a number of memory cells associated with the row address value to a pair of bit lines; each pair of bit lines are associated with a column of memory cells. During a read operation, the bit line pair communicates, to a sense amplifier or other output circuitry, a differential signal corresponding to the data state stored in the memory cell in its associated column which is also in the selected row. Conversely, during a write operation, the bit line pair communicates a differential signal from input circuitry to the memory cell in its associated column which is in the selected row.
An important factor in the performance of a particular memory circuit is the speed at which such read and write operations can be reliably performed. The reliability of such operations is improved where the differential signal communicated by the bit lines is as large as possible. For a read operation, the sense amplifier or other circuit can more accurately read the data state where the differential voltage between the bit lines is large. Especially where the memory cells are fabricated conventionally as cross-coupled inverters with resistive loads (the value of the resistors in the loads being as high as possible, for example on the order of Teraohms), noise immunity of the cell is improved by presentation of a large differential voltage on the bit lines during the write operation. Accordingly, the voltage swing of the bit lines in such memories is preferably as large as possible, occurring in as short a time as possible.
In a write operation for conventional memories, the stability of the data state written into a memory cell depends upon the voltage level applied to the memory cell via the bit lines. As a result, a full rail-to-rail differential voltage on the bit lines will provide the most stable data state possible, so that the written memory cell is tolerant of subsequent reads of its data state, and accesses to neighboring memory cells. However, where a write operation provides a large differential voltage on the bit lines, a subsequent read of a memory cell in the written column (if of the opposite data state from that written), requires that the bit line voltages "recover" from the differential voltage used in the write operation to that of the subsequent read operation. A large differential voltage presented during a write operation will, of course, require a longer period of time for such recovery (and, in turn, a longer access time specification) than in the case of the smaller differential voltage of a read operation.
Conventional static memories have addressed the write recovery problem by precharging and equilibrating the bit lines in the selected columns after a write operation. However, a large differential write voltage will similarly require a longer precharge and equilibration time prior to the subsequent read operation.
Another approach to write recovery is described in Tran, et al., "An 8-ns 256K ECL SRAM with CMOS Memory Array and Battery Backup Capability", J. Solid State Circuits, Vol. 23, No. 5 (IEEE, 1988), pp. 1041-47. In this approach, individual bipolar pull-up transistors are provided for each bit line, the bases of which are controlled by read/write control circuitry, depending upon the state of the input data to the memory. As described in Tran, et al., relative to FIG. 5, the pull-up transistors are controlled so that they are both on during a read operation, pulling the bit lines toward the voltage V.sub.cc -V.sub.be, and so that the pull-up transistor connected to the bit line being pulled low in a write operation is off. An example of the control circuitry for this operation is described in U.S. Pat. No. 4,866,474.
In this described memory, however, these pull-up devices are provided and controlled for each bit line in the memory; as a result, as memory devices become large, the number of such transistors also becomes quite large. Furthermore, the control signals from the read/write control circuitry must be routed to each of the pull-up transistors. In addition, since the pull-up devices are on during a read operation, the memory cell must establish its differential signal on the bit lines in opposition to the loads, slowing the development of the stored data state on the bit lines.
It is therefore an object of this invention to provide a write circuit in a semiconductor memory which assists in the recovery of the bit line voltages following a write operation.
It is a further object of this invention to provide such a circuit which does not require critical timing control of their operation.
It is a further object of this invention to provide such a circuit which also clamps the differential bit line voltage swing for a read operation.
It is a further object of this invention to provide such a circuit which can serve multiple columns in a memory array, without necessarily being placed at each column.
It is a further object of this invention to provide such a circuit which allows for the bit lines to float during the initial portion of a read operation, such that the memory cell can establish differential voltage on the bit lines of its column without opposition from a static or active load.